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HYB18L512320BF-7.5 Datasheet, PDF (15/23 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit SDR Mobile-RAM | |||
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Internet Data Sheet
HY[B/E]18L512320BF-7.5
512-Mbit Mobile-RAM
Parameter
Symbol
- 7.5
Unit Notes1)2)3)4)
Min.
Max.
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
tRRD
15
tRAS
45
tWR
14
tRP
19
â
100k
â
â
ns
8)
ns
8)
ns
9)
ns
8)
Refresh period (8192 rows)
tREF
â
64
ms â
Self refresh exit time
tSREX
1
â
tCK
â
1) 0 °C ⤠TC ⤠70 °C (comm.); -25 °C ⤠TC ⤠85 °C (ext.); VDD = VDDQ = 1.70 V to 1.95 V;
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time tT is measured between VIH and VIL; all AC characteristics assume tT = 1 ns.
5) Specified tAC and tOH parameters are measured with a 30 pF capacity load only as shown in Figure 2.
6) If tT(CLK) > 1 ns, a value of (tT/2 - 0.5) ns has to be added to this parameter.
7) If tT > 1 ns, a value of (tT - 1) ns has to be added to this parameter.
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified
delay / clock period; round up to next integer.
9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when fCK ⤠72 MHz. With fCK > 72 MHz
two clock cycles for tWR are mandatory. Infineon Technologies recommends to use two clock cycles for the write recovery time in all
applications.
I/O
30 pF
FIGURE 2
Measurement with Reference Load
Rev.1.22, 2007-08
15
03292006-D7GM-ZBSS
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