HYB18L512320BF-7.5 Datasheet, PDF (8/23 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit SDR Mobile-RAM

Internet Data Sheet
HY[B/E]18L512320BF-7.5
512-Mbit Mobile-RAM
2
Functional Description
The 512-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally
configured as a quad-bank DRAM.
READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command,
followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select
the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information covering
device initialization, register definition, command description and device operation.
2.1
Register Definition
2.1.1
Mode Register
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes the selection
of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst mode (bit A9). The Mode
Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any
subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
MRMode Register Definition(BA[1:0] = 00_B)
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Field Bits
WB 9
CL [6:4]
Type
w
w
Description
TABLE 5
Mode Register Definition (BA[1:0] = 00_B)
Write Burst Mode
0 Burst Write
1 Single Write
CAS Latency
010 2
011 3
Note: All other bit combinations are RESERVED.
Rev.1.22, 2007-08
8
03292006-D7GM-ZBSS