HYS64T128020EDL Datasheet, PDF (8/43 Pages) Qimonda AG – 200-Pin Small-Outlined DDR2 SDRAM Modules

Pin No.
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
Data Strobe Signals
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
Data Mask Signals
Internet Data Sheet
HYS64T128020EDL–[2.5/3S/3.7]–B
Small Outlined DDR2 SDRAM Modules
Name
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Data Bus 63:0
Note: Data Input / Output pins
DQS0 I/O
DQS0 I/O
DQS1 I/O
DQS1 I/O
DQS2 I/O
DQS2 I/O
DQS3 I/O
DQS3 I/O
DQS4 I/O
DQS4 I/O
DQS5 I/O
DQS5 I/O
DQS6 I/O
DQS6 I/O
DQS7 I/O
DQS7 I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobe Bus 7:0
The data strobes, associated with one data byte, sourced
with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data
window. In Read mode the data strobe is sourced by the
DDR2 SDRAM and is sent at the leading edge of the data
window. DQS signals are complements, and timing is
relative to the cross-point of respective DQS and DQS. If the
module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to V_SS and
DDR2 SDRAM mode registers programmed appropriately.
Rev. 1.12, 2007-10
8
10312006-I253-V1V0