HYS64T128020EDL Datasheet, PDF (36/43 Pages) Qimonda AG – 200-Pin Small-Outlined DDR2 SDRAM Modules

Internet Data Sheet
HYS64T128020EDL–[2.5/3S/3.7]–B
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte#
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Description
t_RAS.MIN [ns]
Module Density per Rank
t_AS.MIN and t_CS.MIN [ns]
t_AH.MIN and t_CH.MIN [ns]
t_DS.MIN [ns]
t_DH.MIN [ns]
t_WR.MIN [ns]
t_WTR.MIN [ns]
t_RTP.MIN [ns]
Analysis Characteristics
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W)
∆T_5B (DT5B)
∆T₇ (DT7)
Psi(ca) PLL
Psi(ca) REG
∆T_PLL (DTPLL)
∆T_REG (DTREG) / Toggle Rate
SPD Revision
HYS64T128020EDL–3.7–B
1 GByte
×64
2 Ranks (×16)
PC2–4200S–444
Rev. 1.2
HEX
2D
80
25
37
10
22
3C
1E
1E
00
06
3C
7F
80
1E
28
00
59
60
3F
2A
2B
20
35
21
40
22
31
00
00
00
00
12
Rev. 1.12, 2007-10
36
10312006-I253-V1V0