HYS64T128020EDL Datasheet, PDF (6/43 Pages) Qimonda AG – 200-Pin Small-Outlined DDR2 SDRAM Modules

Internet Data Sheet
Pin No.
109
Address Signals
107
106
85
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
Data Signals
5
7
17
19
4
6
14
16
23
Rev. 1.12, 2007-10
10312006-I253-V1V0
HYS64T128020EDL–[2.5/3S/3.7]–B
Small Outlined DDR2 SDRAM Modules
Name
WE
Pin
Type
I
Buffer
Type
SSTL
Function
Write Enable
BA0
I
BA1
I
SSTL
SSTL
Bank Address Bus 2:0
Selects which DDR2 SDRAM internal bank of four or eight
is activated.
BA2
I
SSTL Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC SSTL Less than 1Gb DDR2 SDRAMS
A0
I
A1
I
A2
I
A3
I
A4
I
A5
I
A6
I
A7
I
A8
I
A9
I
A10
I
AP
I
A11
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 12:0
During a Bank Activate command cycle, defines the row
address when sampled at the cross-point of the rising edge
of CK and falling edge of CK. During a Read or Write
command cycle, defines the column address when sampled
at the cross point of the rising edge of CK and falling edge
of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If AP is HIGH, autoprecharge is selected and
BA0-BAn defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control
which bank(s) to precharge. If AP is HIGH, all banks will be
precharged regardless of the state of BA0-BAn inputs. If AP
is LOW, then BA0-BAn are used to define which bank to
precharge.
A12
I
SSTL
Address Signal 12
Note: Module based on 256 Mbit or larger dies
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based module
NC
NC —
Not Connected
Note: Module based on 512 Mbit or smaller dies
A14
I
SSTL Address Signal 14
Note: 2 Gbit based module
NC
NC —
Not Connected
Note: Module based on 1 Gbit or smaller dies
DQ0 I/O SSTL Data Bus 63:0
DQ1
I/O
SSTL ^{Note: Data Input / Output pins}
DQ2 I/O SSTL
DQ3 I/O SSTL
DQ4 I/O SSTL
DQ5 I/O SSTL
DQ6 I/O SSTL
DQ7 I/O SSTL
DQ8 I/O SSTL
6