HYS64T128020EDL Datasheet, PDF (16/43 Pages) Qimonda AG – 200-Pin Small-Outlined DDR2 SDRAM Modules

Internet Data Sheet
HYS64T128020EDL–[2.5/3S/3.7]–B
Small Outlined DDR2 SDRAM Modules
Parameter
Symbol DDR2–800
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from
CK / CK
t_IS.BASE
t_LZ.DQ
t_LZ.DQS
MRS command to ODT update delay t_MOD
Mode register set command cycle t_MRD
time
OCD drive mode output delay
t_OIT
DQ/DQS output hold time from DQS t_QH
DQ hold skew factor
t_QHS
Average periodic refresh Interval
t_REFI
Auto-Refresh to Active/Auto-Refresh t_RFC
command period
Precharge-All (8 banks) command t_RP
period
Read preamble
Read postamble
Active to active command period for
2KB page size products
t_RPRE
t_RPST
t_RRD
Internal Read to Precharge command t_RTP
delay
Write preamble
t_WPRE
Write postamble
t_WPST
Write recovery time
t_WR
Internal write to read command delay t_WTR
Exit power down to read command t_XARD
Exit active power-down mode to read t_XARDS
command (slow exit, lower power)
Exit precharge power-down to any t_XP
valid command (other than NOP or
Deselect)
Exit self-refresh to a non-read
command
t_XSNR
Exit self-refresh to read command
Write command to DQS associated
clock edges
t_XSRD
WL
Min.
175
2 x t_AC.MIN
t_AC.MIN
Max.
—
t_AC.MAX
t_AC.MAX
0
12
2
—
0
12
t_HP – t_QHS —
—
300
—
7.8
—
3.9
127.5
—
t_RP + 1 × t_CK —
0.9
1.1
0.4
0.6
10
—
7.5
—
0.35
—
0.4
0.6
15
—
7.5
—
2
—
8 – AL
—
2
—
t_RFC +10
—
200
—
RL – 1
DDR2–667
Min.
200
2 x t_AC.MIN
t_AC.MIN
Max.
—
t_AC.MAX
t_AC.MAX
0
12
2
—
0
12
t_HP – t_QHS —
—
340
—
7.8
—
3.9
127.5
—
t_RP + 1 × t_CK —
0.9
1.1
0.4
0.6
10
—
7.5
—
0.35
—
0.4
0.6
15
—
7.5
—
2
—
7 – AL
—
2
—
t_RFC +10
—
200
—
RL–1
Unit
Note²⁾³⁾⁵
)6)7)8)
ps
24)25)
ps
9)22)
ps
9)22)
ns
35)
nCK
ns
35)
ps
26)
ps
27)
µs
28)29)
µs
28)30)
ns
31)
ns
t_CK.AVG
t_CK.AVG
ns
32)33)
32)34)
35)
ns
35)
t_CK.AVG
t_CK.AVG
ns
ns
35)
35)36)
nCK
nCK
nCK
ns
35)
nCK
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) V_DDQ = 1.8 V ± 0.1V; V_DD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
Rev. 1.12, 2007-10
16
10312006-I253-V1V0