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HYS64T128020EDL Datasheet, PDF (15/43 Pages) Qimonda AG – 200-Pin Small-Outlined DDR2 SDRAM Modules
Internet Data Sheet
HYS64T128020EDL–[2.5/3S/3.7]–B
Small Outlined DDR2 SDRAM Modules
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
3.3.2
Component AC Timing Parameters
Parameter
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Symbol DDR2–800
Min.
Max.
DDR2–667
Min.
Max.
Unit
Note2)3)5
)6)7)8)
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and
low pulse width)
tCCD
tCH.AVG
tCK.AVG
tCKE
Average clock low pulse width
Auto-Precharge write recovery +
precharge time
tCL.AVG
tDAL
Minimum time clocks remain ON after tDELAY
CKE asynchronously drops LOW
DQ and DM input hold time
tDH.BASE
DQ and DM input pulse width for each tDIPW
input
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated
DQ signals
tDQSH
tDQSL
tDQSQ
DQS latching rising transition to
associated clock edges
tDQSS
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
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tDS.BASE
tDSH
tDSS
tFAW
CK half pulse width
tHP
Data-out high-impedance time from
CK / CK
Address and control input hold time
Control & address input pulse width
for each input
tHZ
tIH.BASE
tIPW
2
0.48
2500
3
—
0.52
8000
—
0.48
WR + tnRP
0.52
—
tIS + tCK .AVG ––
+ tIH
125
––
0.35
—
0.35
—
0.35
—
—
200
– 0.25
+ 0.25
50
––
0.2
—
0.2
—
45
—
Min(tCH.ABS,
tCL.ABS)
—
__
tAC.MAX
250
—
0.6
—
2
0.48
3000
3
—
0.52
8000
—
0.48
WR + tnRP
0.52
—
tIS +
––
tCK .AVG + tIH
175
––
0.35
—
0.35
—
0.35
—
—
240
– 0.25
+ 0.25
100
––
0.2
—
0.2
—
50
—
Min(tCH.ABS,
tCL.ABS)
—
__
tAC.MAX
275
—
0.6
—
nCK
tCK.AVG
ps
nCK
10)11)
12)
tCK.AVG
nCK
10)11)
13)14)
ns
ps
15)19)20)
tCK.AVG
tCK.AVG
tCK.AVG
ps
16)
t 17)
CK.AVG
ps
tCK.AVG
tCK.AVG
ns
18)19)20)
17)
17)
35)
ps
21)
ps
9)22)
ps
tCK.AVG
23)25)
Rev. 1.12, 2007-10
15
10312006-I253-V1V0