HYB18M256320CF Datasheet, PDF (7/26 Pages) Qimonda AG – DRAMs for Mobile Applications

Internet Data Sheet
1.4
Pin Definition and Description
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
TABLE 4
Pin Description
Ball
Type Detailed Function
CK, CK
CKE
Input
Input
CS
Input
RAS, CAS,
WE
Input
DQ0 - DQ15 I/O
(x16)DQ0 -
DQ31 (x32)
LDQS, UDQS I/O
(x16)DQS0 -
DQS3 (x32)
LDM, UDM
(x16)DM0 -
DM3 (x32)
Input
BA0, BA1
Input
A0 - A12 (x16) Input
A0 - A11 (x32)
V_DDQ
V_SSQ
V_DD
V_SS
N.C.
Supply
Supply
Supply
Supply
–
Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on
crossing of the positive edge of CK and negative edge of CK.
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides precharge power-down and self refresh
operation (all banks idle), or active power-down (row active in any bank). CKE must be maintained
HIGH throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled
during power-down. Input buffers, excluding CKE are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Data Inputs/Output: Bi-directional data bus
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered with
write data. Used to capture write data.
For x16 LDQS corresponds to the data on DQ0 - DQ7; UDQS to the data on DQ8 - DQ15.
For x32 DQS0 corresponds to the data on DQ0 - DQ7, DQS1 to the data on DQ8 - DQ15, DQS2 to
the data on DQ16 - DQ23, DQS3 to the data on DQ24 - DQ31.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x16
LDM corresponds to the data on DQ0 - DQ7; UDM to the data on DQ8 - DQ15.
For x32 DM0 corresponds to the data on DQ0 - DQ7, DM1 to the data on DQ8 - DQ15, DM2 to the
data on DQ16 - DQ23, DM3 to the data on DQ24 - DQ31.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or
PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be
loaded during a MODE REGISTER SET command (MRS or EMRS).
Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto
Precharge bit for READ/WRITE commands, to select one location out of the memory array in the
respective bank. A10 (=AP) is sampled during a precharge command to determine whether the
PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank is to be
precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-code
during a MODE REGISTER SET command.
I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: V_DDQ = 1.70
V − 1.95 V
I/O Ground
Power Supply: Power for the core logic and input buffers, V_DD = 1.70 V − 1.95 V
Ground
No Connect
Rev.1.44, 2007-07
7
06262007-JK8G-48BV