HYB18M256320CF Datasheet, PDF (17/26 Pages) Qimonda AG – DRAMs for Mobile Applications

Internet Data Sheet
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
Parameter
Symbol
–6
Min.
Max.
– 7.5
Min.
Max.
Unit Note
1)2)3)4)
Read preamble
CL = 3
CL = 2
t_RPRE
0.9
1.1
–
–
0.9
1.1
0.5
1.1
t_CK ²⁰⁾
Read postamble
t_RPST
0.4
0.6
ACTIVE to PRECHARGE command period
t_RAS
42
70k
ACTIVE to ACTIVE command period
t_RC
60
–
AUTO REFRESH to ACTIVE/AUTO REFRESH t_RFC
72
–
command period
0.4
0.6
45
70k
67
–
75
–
t_CK –
ns ²¹⁾
ns ²²⁾
ns ²²⁾
ACTIVE to READ or WRITE delay
t_RCD
Col address to col address delay
t_CCD
PRECHARGE command period
t_RP
ACTIVE bank A to ACTIVE bank B delay
t_RRD
WRITE recovery time
t_WR
Auto precharge write recovery + precharge time t_DAL
Internal write to Read command delay
t_WTR
Self refresh exit to next valid command delay
t_XSR
Exit power down delay
t_XP
CKE minimum low time
t_CKE
Refresh period
t_REF
Average periodic refresh interval
t_REFI
18
–
22.5 –
ns ²²⁾
1
–
18
–
1
–
22.5 –
t_CK
ns ²²⁾
12
–
15
–
ns ²²⁾
15
–
15
–
ns ²²⁾
(t_WR/t_CK) + (t_RP/t_CK)
1
–
1
–
120
–
120
–
t_CK ²²⁾
t_CK ²³⁾
ns ²²⁾
t_CK + t_IS –
2
–
–
64
t_CK + t_IS –
2
–
–
64
ns –
t_CK –
ms
–
7.8 (× 16) –
7.8 (× 16) µs ²⁴⁾
15.6 (x32)
15.6 (x32)
1) 0 °C ≤ T_C ≤ 70 °C (comm.); -25°C ≤ T_C ≤ 85 °C (ext.);V_DD = 1.70 V - 1.95 V, V_DDQ = 1.70 V - 1.95 V. All voltages referenced to V_SS.
2) All parameters assume proper device initialization.
3) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK; the input reference level for signals
other than CK/CK is V_DDQ/2.
4) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
5) The output timing reference level is V_DDQ/2.
6) Parameters t_AC and t_QH are specified for full drive strength and a reference load see Figure 3. This circuit is not intended to be either a
precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive
strength with a nominal load of 10pF parameters t_AC and t_QH are expected to be in the same range. However, these parameters are not
subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is
suggested.
7) Min (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for t_CL and t_CH).
8) t_QH = t_HP - t_QHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (t_CL, t_CH). t_QHS accounts
for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
9) DQ, DM and DQS input slew rate is measured between V_ILD(DC) and V_IHD(AC) (rising) or V_IHD(DC) and V_ILD(AC) (falling).
10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
11) Input slew rate ≥ 1.0 V/ns.
12) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test.
14) The transition time for address and command inputs is measured between V_IH and V_IL.
15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
16) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Rev.1.44, 2007-07
17
06262007-JK8G-48BV