HYS72T64400HFA Datasheet, PDF (6/47 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
2
Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns
Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
Pin#
Nam Pin
e
Type
Clock Signals
228
SCK I
229
SCK I
Control Signals
17
RES I
ET
Northbound
22
PN0 O
25
PN1 O
28
PN2 O
31
PN3 O
34
PN4 O
37
PN5 O
51
PN6 O
54
PN7 O
57
PN8 O
60
PN9 O
63
PN10 O
66
PN11 O
48
PN12 O
40
PN13 O
23
PN0 O
26
PN1 O
29
PN2 O
32
PN3 O
35
PN4 O
38
PN5 O
52
PN6 O
55
PN7 O
58
PN8 O
61
PN9 O
64
PN10 O
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
Buffer
Type
Function
TABLE 5
Pin Configuration of FB-DIMM
HSDL_15
HSDL_15
System Clock Input, positive line
System Clock Input, negative line
LV-CMOS AMB reset signal
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Primary Northbound Data, positive lines
6