HYS72T64400HFA Datasheet, PDF (20/47 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.
4. Burst Length = 4.
5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).
6. Modeled with 27 Ω termination for command, address, and clocks, and 47 Ω termination for control.
7. Termination is referenced to V_TT = V_DD / 2.
Rev.1.01, 2007-06-20
20
10062006-RQWY-GI6S