HYS72T64400HFA Datasheet, PDF (26/47 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Product Type
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Organization
512MB
1 GByte
2 GByte
×72
×72
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–6400F–666 PC2–6400F–666 PC2–6400F–666
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Description
HEX
CAS Latencies Supported
43
t_CAS.MIN (min. CAS Latency Time)
3C
Write Recovery Values Supported (WR)
52
t_WR.MIN (Write Recovery Time)
3C
Write Latency Times Supported
92
Additive Latency Times Supported
60
t_RCD.MIN (min. RAS# to CAS# Delay)
3C
t_RRD.MIN (min. Row Active to Row Active Delay)
1E
t_RP.MIN (min. Row Precharge Time)
3C
t_RAS and t_RC Extension
00
t_RAS.MIN (min. Active to Precharge Time)
B4
t_RC.MIN (min. Active to Active / Refresh Time)
DC
t_RFC.MIN LSB (min. Refresh Recovery Time Delay)
A4
t_RFC.MIN MSB (min. Refresh Recovery Time Delay)
01
t_WTR.MIN (min. Internal Write to Read Cmd Delay)
1E
t_RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
03
Terminations Supported
07
Drive Strength Supported
01
t_REFI (avg. SDRAM Refresh Period)
C2
T_CASE.MAX Delta / ∆T_4R4W Delta
50
Psi(T-A) DRAM
7A
∆T₀ (DT0) DRAM
58
∆T_2Q (DT2Q) DRAM
34
∆T_2P (DT2P) DRAM
36
∆T_3N (DT3N) DRAM
2E
HEX
43
3C
52
3C
92
60
3C
1E
3C
00
B4
DC
A4
01
1E
1E
03
07
01
C2
50
7A
58
34
36
2E
HEX
43
3C
52
3C
92
60
3C
1E
3C
00
B4
DC
A4
01
1E
1E
03
07
01
C2
50
7A
58
34
36
2E
Rev.1.01, 2007-06-20
26
10062006-RQWY-GI6S