HYS64T32X00HDL_07 Datasheet, PDF (6/69 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
2
Pin Configurations
2.1
Pin Configurations
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations
used in columns Pin Type and Buffer Type are explained in Table 6 and Table 7 respectively. The Pin numbering is depicted
in Figure 1
Pin No.
Clock Signals
30
164
32
166
79
80
Control Signals
110
115
108
113
Name Pin Buffer Function
Type Type
TABLE 5
Pin Configuration of SO-DIMM
CK0
I
CK1
I
CK0
I
CK1
I
CKE0 I
CKE1 I
NC
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Clock Signals 1:0, Complement Clock Signals 1:0
The system clock inputs. All address and command lines
are sampled on the cross point of the rising edge of CK and
the falling edge of CK. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
Clock Enable Rank 1:0
Activates the DDR2 SDRAM CK signal when HIGH and
deactivates the CK signal when LOW. By deactivating the
clocks, CKE LOW initiates the Power Down Mode or the
Self Refresh Mode.
Note: 2 Ranks module
Not Connected
Note: 1-rank module
S0
S1
NC
RAS
CAS
I
SSTL Chip Select Rank 1:0
I
SSTL ^{Enables the associated DDR2 SDRAM command decoder}
when LOW and disables the command decoder when
HIGH. When the command decoder is disabled, new
commands are ignored but previous operations continue.
Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks
are also called "Physical banks".2 Ranks module
NC —
Not Connected
Note: 1-rank module
I
SSTL Row Address Strobe
When sampled at the cross point of the rising edge of CK,
and falling edge of CK, RAS, CAS and WE define the
operation to be executed by the SDRAM.
I
SSTL Column Address Strobe
Rev. 1.12, 2007-10
6
03292006-5LTN-QML0