HYS64T32X00HDL_07 Datasheet, PDF (15/69 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
3.3
Timing Characteristics
3.3.1
Speed Grade Definitions
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Period
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Symbol
t_CK
t_CK
t_CK
t_CK
t_RAS
t_RC
t_RCD
t_RP
DDR2–800D
–25F
5–5–5
Min.
5
3.75
2.5
2.5
45
57.5
12.5
12.5
Max.
8
8
8
8
70k
—
—
—
DDR2–800E
–2.5
6–6–6
Min.
5
3.75
3
2.5
45
60
15
15
Max.
8
8
8
8
70k
—
—
—
TABLE 12
Speed Grade Definition
Unit
Note
t_CK
—
ns
1)2)3)4)
ns
1)2)3)4)
ns
1)2)3)4)
ns
1)2)3)4)
ns
1)2)3)4)5)
ns
1)2)3)4)
ns
1)2)3)4)
ns
1)2)3)4)
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Period @ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
DDR2–667C
–3
4–4–4
Symbol Min.
t_CK
5
t_CK
3
t_CK
3
t_RAS
45
t_RC
57
t_RCD
12
t_RP
12
Max.
8
8
8
70k
—
—
—
DDR2–667D
–3S
5–5–5
Min. Max.
5
8
3.75 8
3
8
45
70k
60
—
15
—
15
—
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
Max.
8
8
8
70k
—
—
—
TABLE 13
Speed Grade Definition
DDR2–400B Unit Note
–5
3–3–3
t_CK
Min. Max. —
5
8
ns
5
8
ns
5
8
ns
40
70k ns
55
— ns
15
— ns
15
— ns
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) mentioned in Component datasheet.
Rev. 1.12, 2007-10
15
03292006-5LTN-QML0