HYS64T32X00HDL_07 Datasheet, PDF (21/69 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Parameter
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400
Symbol
DDR2–533
Min.
Max.
DDR2–400
Min.
Max.
Unit
Notes²⁾³⁾
4)5)6)7)
CAS A to CAS B command period t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse t_CKE
width
CK, CK low-level width
t_CL
Auto-Precharge write recovery + t_DAL
precharge time
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
t_DELAY
DQ and DM input hold time
(differential data strobe)
t_DH.BASE
DQ and DM input hold time (single t_DH1.BASE
ended data strobe)
DQ and DM input pulse width (each t_DIPW
input)
DQS input HIGH pulse width (write t_DQSH
cycle)
DQS input LOW pulse width (write t_DQSL
cycle)
DQS-DQ skew (for DQS &
associated DQ signals)
t_DQSQ
Write command to 1st DQS latching t_DQSS
transition
DQ and DM input setup time
(differential data strobe)
t_DS.BASE
DQ and DM input setup time (single t_DS1.BASE
ended data strobe)
DQS falling edge hold time from CK t_DSH
(write cycle)
DQS falling edge to CK setup time t_DSS
(write cycle)
Four Activate Window period
t_FAW
Four Activate Window period
t_FAW
Clock half period
t_HP
Data-out high-impedance time from t_HZ
CK / CK
Address and control input hold time
Address and control input pulse
width
(each input)
t_IH.BASE
t_IPW
2
—
0.45
0.55
3
—
0.45
WR + t_RP
0.55
—
t_IS + t_CK + t_IH ––
225
––
–25
—
0.35
—
0.35
—
0.35
—
—
300
– 0.25
+ 0.25
100
—
–25
—
0.2
—
0.2
—
37.5
—
50
—
MIN. (t_CL, t_CH)
—
t_AC.MAX
375
—
0.6
—
2
—
0.45
0.55
3
—
0.45
WR + t_RP
0.55
—
t_IS + t_CK + t_IH ––
275
––
25
—
0.35
—
0.35
—
0.35
—
—
350
– 0.25
+ 0.25
150
—
25
—
0.2
—
0.2
—
37.5
—
50
—
MIN. (t_CL, t_CH)
—
t_AC.MAX
475
—
0.6
—
t_CK
t_CK
t_CK
t_CK
t_CK
8)
ns
9)
ps
10)
ps
11)
t_CK
t_CK
t_CK
ps
11)
t_CK
ps
11)
ps
11)
t_CK
t_CK
ns
ns
13)
12)
ps
13)
ps
11)
t_CK
Rev. 1.12, 2007-10
21
03292006-5LTN-QML0