HYS64T32X00HDL_07 Datasheet, PDF (22/69 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
Address and control input setup time t_IS.BASE
DQ low-impedance time from CK / t_LZ(DQ)
CK
DQS low-impedance from CK / CK
MRS command to ODT update
delay
t_LZ(DQS)
t_MOD
Mode register set command cycle t_MRD
time
OCD drive mode output delay
t_OIT
Data output hold time from DQS t_QH
Data hold skew factor
t_QHS
Average periodic refresh Interval t_REFI
Average periodic refresh Interval t_REFI
Auto-Refresh to Active/Auto-
t_RFC
Refresh command period
Precharge-All (4 banks) command t_RP
period
Read preamble
Read postamble
Active bank A to Active bank B
command period
t_RPRE
t_RPST
t_RRD
Active bank A to Active bank B
t_RRD
command period
Internal Read to Precharge
t_RTP
command delay
Write preamble
Write postamble
Write recovery time for write without
Auto-Precharge
t_WPRE
t_WPST
t_WR
Internal Write to Read command t_WTR
delay
Exit power down to any valid
command
(other than NOP or Deselect)
t_XARD
Exit active power-down mode to
Read command (slow exit, lower
power)
t_XARDS
Exit precharge power-down to any t_XP
valid command (other than NOP or
Deselect)
Exit Self-Refresh to non-Read
command
t_XSNR
DDR2–533
Min.
250
2 × t_AC.MIN
Max.
—
t_AC.MAX
t_AC.MIN
0
t_AC.MAX
12
2
—
0
12
t_HP –t_QHS
—
—
400
—
7.8
—
3.9
105
—
t_RP
—
0.9
1.1
0.40
0.60
7.5
—
10
—
7.5
—
0.25
—
0.40
0.60
15
—
7.5
—
2
—
6 – AL
—
2
—
t_RFC +10
—
DDR2–400
Min.
350
2 × t_AC.MIN
Max.
—
t_AC.MAX
t_AC.MIN
0
t_AC.MAX
12
2
—
0
12
t_HP –t_QHS
—
—
450
—
7.8
—
3.9
105
—
t_RP
—
0.9
1.1
0.40
0.60
7.5
—
10
—
7.5
—
0.25
—
0.40
0.60
15
—
10
—
2
—
6 – AL
—
2
—
t_RFC +10
—
Unit
Notes²⁾³⁾
4)5)6)7)
ps
11)
ps
14)
ps
14)
ns
t_CK
ns
ps
µs
14)15)
µs
16)18)
ns
17)
ns
t_CK
14)
t_CK
14)
ns
14)18)
ns
16)22)
ns
t_CK
t_CK
19)
ns
ns
20)
t_CK
21)
t_CK
21)
t_CK
ns
Rev. 1.12, 2007-10
22
03292006-5LTN-QML0