HYS64T32X00HDL_07 Datasheet, PDF (25/69 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from t_AOFD. Both are measured from t_AOFD, which is interpreted differently per speed bin. For DDR2-400/533, t_AOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if t_CK = 5 ns.
3.4
I_DD Specifications and Conditions
List of tables defining I_DD Specifications and Conditions.
Parameter
TABLE 18
I_DD Measurement Conditions
Symbol Note¹⁾²⁾
3)4)5)
Operating Current 0
I_DD0
One bank Active - Precharge; t_CK = t_CK.MIN, t_RC = t_RC.MIN, t_RAS = t_RAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
I_DD1
6)
One bank Active - Read - Precharge; I_OUT = 0 mA, BL = 4, t_CK = t_CK.MIN, t_RC = t_RC.MIN, t_RAS = t_RAS.MIN,
t_RCD = t_RCD.MIN, AL = 0, CL = CL_MIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
I_DD2N
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
I_DD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
I_DD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CK.MIN;
t_RAS = t_RAS.MAX, t_RP = t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; I_OUT = 0 mA.
Active Power-Down Current
All banks open; t_CK = t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
I_DD3N
I_DD3P(0)
Active Power-Down Current
I_DD3P(1)
All banks open; t_CK = t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
I_DD4R
6)
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CKMIN; t_RAS = t_RASMAX;
t_RP = t_RPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; I_OUT = 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CK.MIN;
t_RAS = t_RAS.MAX., t_RP = t_RP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I_DD4W
Burst Refresh Current
t_CK = t_CK.MIN., Refresh command every t_RFC = t_RFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I_DD5B
Rev. 1.12, 2007-10
25
03292006-5LTN-QML0