HYS64T32X00HDL_07 Datasheet, PDF (19/69 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
27) t_QHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
29) 0 °C≤ T_CASE ≤ 85 °C.
30) 85 °C < T_CASE ≤ 95 °C.
31) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
32) t_RPST end point and t_RPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(t_RPST), or begins driving (t_RPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (t_RPST), or begins
driving (t_RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.PER.MIN = – 72 ps
t t t t t t t and _JIT.PER.MAX = + 93 ps, then _{RPRE.MIN(DERATED)} = _RPRE.MIN + _JIT.PER.MIN = 0.9 x _CK.AVG – 72 ps = + 2178 ps and _{RPRE.MAX(DERATED)} = _RPRE.MAX
+ t_JIT.PER.MAX = 1.1 x t_CK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
34) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.DUTY.MIN = – 72 ps
t t t t t t t and _JIT.DUTY.MAX = + 93 ps, then _{RPST.MIN(DERATED)} = _RPST.MIN + _JIT.DUTY.MIN = 0.4 x _CK.AVG – 72 ps = + 928 ps and _{RPST.MAX(DERATED)} = _RPST.MAX
+ t_JIT.DUTY.MAX = 0.6 x t_CK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
35) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM = RU{t_PARAM / t_CK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP = RU{t_RP / t_CK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP = 15 ns, the device will support
t_nRP = RU{t_RP / t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
36) t_WTR is at lease two clocks (2 x t_CK) independent of operation frequency.
FIGURE 2
Method for calculating transitions and endpoint
W+=
W536 7 H QG SRLQW
92+ [P9 
92+ [P9 
92/ [P9 
92/ [P9 
7 7
W+=W536 7 HQG SRLQ W  77 
977[P9
977[P9
977[P 9
977[P9
W/=
W53 5(EHJLQSRLQW
7 7
W/=W535( E HJLQ SRLQ W  7 7 
Rev. 1.12, 2007-10
19
03292006-5LTN-QML0