HYS72D64301HBR_07 Datasheet, PDF (5/39 Pages) Qimonda AG – 184-Pin Registered Double-Data-Rate SDRAM Module

Internet Data Sheet
HYS72D[64/128/256]xxxHBR–[5/6]–C
Registered Double-Data-Rate SDRAM Module
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used
in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Chapter 1.
TABLE 4
Pin Configuration of RDIMM
Pin Name Pin Buffer Function
#
Type Type
Clock Signals
137 CK0 I
138 CK0 I
21 CKE0 I
111 CKE1 I
NC
NC
Control Signals
157 S0
I
158 S1
I
NC
NC
154 RAS I
65 CAS I
63 WE
I
10 RESET I
Address Signals
59 BA0 I
52 BA1 I
48 A0
I
43 A1
I
41 A2
I
130 A3
I
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Signal
Complement Clock
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
SSTL Chip Select of Rank 0
SSTL Chip Select of Rank 1
Note: 2-ranks module
–
Note: 1-rank module
SSTL Row Address Strobe
SSTL Column Address Strobe
SSTL Write Enable
LV- Register Reset
CMOS Forces registered inputs
low
Note: For detailed des-
cription of the
Power Up and
Power
Management see
the Application
Note at the end of
data sheet
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Address Bus 11:0
Pin Name
#
37 A4
32 A5
125 A6
29 A7
122 A8
27 A9
141 A10
AP
118 A11
115 A12
NC
167 A13
NC
Data Signals
2 DQ0
4 DQ1
6 DQ2
8 DQ3
94 DQ4
95 DQ5
98 DQ6
99 DQ7
12 DQ8
13 DQ9
19 DQ10
20 DQ11
105 DQ12
Pin
Type
I
I
I
I
I
I
I
I
I
I
NC
I
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
SSTL
–
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Address Bus 11:0
Address Signal 12
Note: Module based on
256 Mbit or larger
dies
Note: 128 Mbit based
module
Address Signal 13
Note: 1 Gbit based
module
Note: Module based on
512 Mbit or smaller
dies
Data Bus 63:0
Rev. 1.22, 2007-08
5
03292006-6N25-8R3I