HYS72D64301HBR_07 Datasheet, PDF (4/39 Pages) Qimonda AG – 184-Pin Registered Double-Data-Rate SDRAM Module

Internet Data Sheet
HYS72D[64/128/256]xxxHBR–[5/6]–C
Registered Double-Data-Rate SDRAM Module
1.2
Description
The HYS72D[64/128/256]xxxHBR–[5/6]–C are low-profile
versions of the standard Registered DIMM modules with 1.1-
inch (28.58 mm) and 1.2-inch (30.40 mm) height for Server
Applications. The low-profile DIMM versions are available as
64M ×72 (512MB), 128M ×72 (1 GB), and 256M ×72 (2 GB).
The memory array is designed with Double-Data-Rate
Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. A variety of decoupling capacitors are
mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E²PROM device using the
2-pin I²C protocol. The first 128 bytes contain factory
programmed configuration data and the second 128 bytes
are made available to the customer.
Product Type¹⁾
Compliance Code²⁾ Description
TABLE 2
Ordering Information
SDRAM Technology
PC3200 (CL=3)
HYS72D64301HBR–5–C PC3200R–30331–A0 one rank 512 MByte Reg. ECC DIMM
512 MBit (×8)
HYS72D128300HBR–5–C PC3200R–30331–C0 one rank 1 GByte Reg. ECC DIMM
512 MBit (×4)
HYS72D128321HBR–5–C PC3200R–30331–B0 two ranks 1 GByte Reg. ECC DIMM
512 MBit (×8)
HYS72D256320HBR–5–C PC3200R–30331–F0 two ranks 2 GByte Reg. ECC DIMM
512 MBit (×4)
PC2700 (CL=2.5)
HYS72D64301HBR–6–C PC2700R–25331–A0 one rank 512 MByte Reg. ECC DIMM
512 MBit (×8)
HYS72D128300HBR–6–C PC2700R–25331–C0 one rank 1 GByte Reg. ECC DIMM
512 MBit (×4)
HYS72D128900HBR–6–C PC2700R–25331–C0 one rank 1 GByte Reg. ECC DIMM
512 MBit (×4)
HYS72D128321HBR–6–C PC2700R–25331–B0 two ranks 1 GByte Reg. ECC DIMM
512 MBit (×8)
HYS72D256320HBR–6–C PC2700R–25331–F0 two ranks 2 GByte Reg. ECC DIMM
512 MBit (×4)
HYS72D256920HBR–6–C PC2700R–25331–F0 two ranks 2 GByte Reg. ECC DIMM
512 MBit (×4)
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example:
HYS72D256320HBR–5–C, indicating Rev.C die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC2700R”), the latencies (for example
“25331” means CAS latency of 2.5 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), SPD
code definition version 1, and the Raw Card used for this module.
Density Organization
512 MB
1 GB
1 GB
2 GB
64M ×72
128M ×72
128M ×72
256M ×72
Memory
Ranks
1
1
2
2
SDRAMs
64M ×8
128M ×4
64M ×8
128M ×4
# of
SDRAMs
9
18
18
36
# of row/bank/
column bits
13/2/11
13/2/12
13/2/11
13/2/12
Refresh
TABLE 3
Address Format
Period Interval
8K
64 ms 7.8 ms
8K
64 ms 7.8 ms
8K
64 ms 7.8 ms
8K
64 ms 7.8 ms
Rev. 1.22, 2007-08
4
03292006-6N25-8R3I