HYS72D64301HBR_07 Datasheet, PDF (37/39 Pages) Qimonda AG – 184-Pin Registered Double-Data-Rate SDRAM Module

Internet Data Sheet
HYS72D[64/128/256]xxxHBR–[5/6]–C
Registered Double-Data-Rate SDRAM Module
2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands.
Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register
inputs must continue to remain stable).
3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation
time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable.
During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that
the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a
low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are
stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive
a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this
application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input
into the register clock input. Without the low level on RESET an unknown DIMM state will result.
Rev. 1.22, 2007-08
37
03292006-6N25-8R3I