HYS72D64301HBR_07 Datasheet, PDF (36/39 Pages) Qimonda AG – 184-Pin Registered Double-Data-Rate SDRAM Module

Internet Data Sheet
HYS72D[64/128/256]xxxHBR–[5/6]–C
Registered Double-Data-Rate SDRAM Module
• The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not
assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system
clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM
PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE
must be maintained low and all other inputs should be driven to a known state. In general these commands can be
determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with CKE low), as this is the first
command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a ‘NOP Deselect’ command). A second
option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level. The SDRAM is now functional and prepared to receive commands.
Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this
period, register inputs must remain stable).
4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation
time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable.
During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that
the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level
on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are
stable and ready to accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an
alternate operating mode for these DIMMs.
1. System enters Self Refresh entry command. (CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM.
After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are
Don’t Cares — with the exception of CKE.
• The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of
the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
• The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of
the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals
must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low
during the operation.
• The DIMM is in a low power, Self Refresh mode.
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE
must be maintained low and all other inputs should be driven to a known state. In general these commands can be
determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with CKE low), as this is the first
command defined by the Self Refresh Exit sequence (ideally this would be a ‘NOP Deselect’ command). A second option
is to apply low levels on all of the register inputs to be consistent with the state of the register outputs.
Rev. 1.22, 2007-08
36
03292006-6N25-8R3I