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HYS72D64301HBR_07 Datasheet, PDF (11/39 Pages) Qimonda AG – 184-Pin Registered Double-Data-Rate SDRAM Module
Internet Data Sheet
HYS72D[64/128/256]xxxHBR–[5/6]–C
Registered Double-Data-Rate SDRAM Module
Parameter
Symbol
TABLE 8
Electrical Characteristics and DC Operating Conditions
Values
Unit Note/Test Condition1)
Min.
Typ.
Max.
Device Supply Voltage
VDD
2.3
Device Supply Voltage
VDD
2.5
Output Supply Voltage
VDDQ
2.3
Output Supply Voltage
VDDQ
2.5
EEPROM supply voltage
VDDSPD
2.3
Supply Voltage, I/O Supply VSS, VSSQ 0
Voltage
2.5
2.7
2.6
2.7
2.5
2.7
2.6
2.7
2.5
3.6
0
V fCK ≤ 166 MHz
V
fCK > 166 MHz 2)
V
fCK ≤ 166 MHz 3)
V
fCK > 166 MHz 2)3)
V—
V—
Input Reference Voltage
I/O Termination Voltage
(System)
VREF
VTT
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V
4)
VREF – 0.04
VREF + 0.04 V
5)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level, CK and
CK Inputs
VIH(DC)
VIL(DC)
VIN(DC)
VREF + 0.15
–0.3
–0.3
VDDQ + 0.3 V
6)
VREF – 0.15 V
6)
VDDQ + 0.3 V
6)
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6 V
6)7)
VI-Matching Pull-up Current VIRatio
to Pull-down Current
0.71
1.4
— 8)
Input Leakage Current
II
–2
2
µA Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V9)
Output Leakage Current
IOZ
–5
Output High Current, Normal IOH
—
Strength Driver
5
–16.2
µA DQs are disabled; 0 V ≤ VOUT ≤
VDDQ 9)
mA VOUT = 1.95 V
Output Low Current, Normal IOL
16.2
Strength Driver
—
mA VOUT = 0.35 V
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V;
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF.DC. VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
6) Inputs are not recognized as valid until VREF stabilizes.
7) VID is the magnitude of the difference between the input level on CK and the input level on CK.
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
9) Values are shown per pin.
Rev. 1.22, 2007-08
11
03292006-6N25-8R3I