HYB18T512400B Datasheet, PDF (42/68 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0B[C/F]
512-Mbit Double-Data-Rate-Two SDRAM
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
Speed Grade
TABLE 46
Speed Grade Definition Speed Bins for DDR2-400B
DDR2–400B
Unit
Note
QAG Sort Name
–5
CAS-RCD-RP latencies
3–3–3
t_CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
@ CL = 3
@ CL = 4
@ CL = 5
t_CK
t_CK
t_CK
t_RAS
t_RC
t_RCD
t_RP
5
8
ns
1)2)3)4)
5
8
ns
1)2)3)4)
5
8
ns
1)2)3)4)
40
70000
ns
1)2)3)4)5)
55
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0).
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
4) The output timing reference voltage level is V_TT. See section 8 for the reference load for timing measurements.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
Rev. 1.1, 2007-05
42
03292006-YBYM-WG0Z