HYB18T512400B Datasheet, PDF (14/68 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0B[C/F]
512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 2
Chip Configuration for ×8 components, PG-TFBGA-60 (top view)
9_{'' 1&5'46} 9₆₆
$
'4
9_{664 '05'46}
%
9_''4
'4
9_''4
&
'4
9₆₆₄
'4
'
9_''/
9₅₍₎
9₆₆
(
&.( :(
)
1&%$ %$ %$
*
$$3 $
+
9₆₆
$
$
-
$
$
.
9_''
$
1&
/
9₆₆₄
'46
9_''4
'46
9₆₆₄
'4
9_''4
'4
9_''4
'4
9₆₆₄
'4
9_66'/
&.
9_''
5$6 &. 2'7
&$6 &6
$
$
9_''
$
$
$
$
9₆₆
1& 1&$
0337
Notes
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is disabled
3. When enabled, RDQS & RDQS are used as strobe
signals during reads.
4. V_DDL and V_SSDL are power and ground for the DLL. V_DDL is
connected to V_DD on the device. V_DD, V_DDQ, V_SSDL, V_SS,
and V_SSQ are isolated on the device.
5. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit.
Rev. 1.1, 2007-05
14
03292006-YBYM-WG0Z