HYB18T512400B Datasheet, PDF (13/68 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0B[C/F]
512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration for ×4 components, PG-TFBGA-60 (top view)









6_'' 1& 6_{6 6}
$
6_664 '46  6_''4
1& 6_{6 64 } '0
%
'46 6_{6 64} 1&
6_{' '4} '4 6_{' '4}
&
6_''4 '4 6_''4
1& 6_{6 64 } '4
'
'4 6_{6 64} 1&
6_''/ 6_{5 ()} 6_{6 6}
(
9_66'/ &.
6_{' '}
&.( :(
)
5$6 &. 2'7
1& %$ %$
*
&$6 &6
$$ 3 $
+
$
$ 6_{' '}
6_{6 6}
$
$
-
$ $
$ $
.
$ $ 6_{6 6}
6_'' $ 1&
/
1& 1& $ 
0337 
Notes
1. V_DDL and V_SSDL are power and ground for the DLL. V_DDL is
connected to V_DD on the device. V_DD, V_DDQ, V_SSDL, V_SS,
and V_SSQ are isolated on the device.
2. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit
Rev. 1.1, 2007-05
13
03292006-YBYM-WG0Z