HYB18T512400B Datasheet, PDF (19/68 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0B[C/F]
512-Mbit Double-Data-Rate-Two SDRAM
Field Bits Type¹⁾
Description
CL
[6:4] w
CAS Latency
Note: All other bit combinations are illegal.
BT
3
w
BL
[2:0] w
011_B CL 3
100_B CL 4
101_B CL 5
110_B CL 6
111_B CL 7
Burst Type
0_B BT Sequential
1_B BT Interleaved
Burst Length
Note: All other bit combinations are illegal.
010_B BL 4
011_B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t_WR (in ns) by t_CK (in ns) and
rounding up to the next integer: WR [cycles] ≥ t_WR (ns) / t_CK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue t_WR timing WR_MIN is determined by t_CK.MAX and WR_MAX is determined by t_CK.MIN.
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Field
BA2
Bits Type¹⁾
16 reg. addr.
BA1
15
BA0
14
A13
13 w
Qoff
12 w
RDQS 11 w
Description
TABLE 14
Extended Mode Register Definition (BA[2:0] = 001_B)
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0_B BA2 Bank Address
Bank Address [1]
0_B BA1 Bank Address
Bank Address [0]
1_B BA0 Bank Address
Address Bus [13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0_B A13 Address bit 13
Output Disable
0_B QOff Output buffers enabled
1_B QOff Output buffers disabled
Read Data Strobe Output (RDQS, RDQS)
0_B RDQS Disable
1_B RDQS Enable
Rev. 1.1, 2007-05
19
03292006-YBYM-WG0Z