HYB18T512400B Datasheet, PDF (3/68 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
1
Overview
HYB18T512[40/80/16]0B[C/F]
512-Mbit Double-Data-Rate-Two SDRAM
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• 1.8 V ± 0.1 V Power Supply
1.8 V ± 0.1 V (SSTL_18) compatible I/O
• DRAM organizations with 4 and 8 data in/outputs
• Double-Data-Rate-Two architecture: two data transfers
per clock cycle four internal banks for concurrent operation
• Programmable CAS Latency: 3, 4, 5 and 6
• Programmable Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe
operation
• Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
command and data bus efficiency
• Off-Chip-Driver impedance adjustment (OCD) and On-
Die-Termination (ODT) for better signal quality
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-
Down modes
• Average Refresh Period 7.8 µs at a T_CASE lower than
85 °C, 3.9 µs between 85 °C and 95 °C
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
• 1kB page size for ×4 & ×8, 2kB page size for ×16
• Package: P(G)-TFBGA-60 and P(G)-TFBGA-84
• RoHS Compliant Products¹⁾
• All Speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications when run at a clock rate
of 200 MHz.
Product Type Speed Code
–25F
Speed Grade
DDR2–800D 5–5–5
Max. Clock Frequency @CL6 f_CK6 400
@CL5 f_CK5 400
@CL4 f_CK4 266
@CL3 f_CK3 200
Min. RAS-CAS-Delay
t_RCD 12.5
Min. Row Precharge Time
t_RP 12.5
Min. Row Active Time
t_RAS 45
Min. Row Cycle Time
t_RC 57.5
TABLE 1
Performance Table for –25F and –2.5
–2.5
Unit
DDR2–800E 6–6–6
400
333
266
200
15
15
45
60
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.1, 2007-05
3
03292006-YBYM-WG0Z