HYS72T128001HR Datasheet, PDF (4/40 Pages) Qimonda AG – 240-Pin Registered DDR SDRAM Modules

Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS72T[128/256]00xHR–[3S/3.7/5]–A module
family are Registered DIMM modules with 30,0 mm height
based on DDR2 technology. DIMMs are available as ECC
modules in 128M ×72 (1 GByte) and 256M ×72 (2 GByte)
organization and density, intended for mounting into 240-Pin
connector sockets.
The memory array is designed with 1-Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. All control and address
signals are re-driven on the DIMM using register devices and
a PLL for the clock distribution. This reduces capacitive
loading to the system bus, but adds one cycle to the SDRAM
timing. Decoupling capacitors are mounted on the PCB
board. The DIMMs feature serial presence detect based on a
serial E²PROM device using the 2-pin I²C protocol. The first
128 bytes are programmed with configuration data and the
second 128 bytes are available to the customer.
Product Type¹⁾
Compliance Code²⁾
TABLE 2
Ordering Information for RoHS Compliant Products
Description
SDRAM Technology
PC2–5300
HYS72T256000HR–3S–A 2GB 1Rx4 PC2–5300R–444–11–H0
1 Rank, ECC
1 Gbit (×4)
PC2–4200
HYS72T256000HR–3.7–A 2GB 1Rx4 PC2–4200R–444–11–H0
1 Rank, ECC
1 Gbit (×4)
PC2–3200
HYS72T128001HR–5–A
1GB 1Rx8 PC2–3200R–333–12–F0
1 Rank, ECC
1 Gbit (×8)
HYS72T256000HR–5–A
2GB 1Rx4 PC2–3200R–333–11–H0
1 Rank, ECC
1 Gbit (×4)
1) All Product Types end with a place code, designating the silicon die revision. Example: HYS72T256000HR–3.7–A, indicating Rev. “A” dies
are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–H0”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and
produced on the Raw Card “F”
DIMM
Density
1 GB
2 GB
Module
Organization
128M ×72
256M ×72
Memory
Ranks
1
1
ECC/
Non-ECC
ECC
ECC
TABLE 3
Address Format
# of SDRAMs # of row/bank/column
bits
Raw
Card
9
14/3/11
A-F
18
14/3/11
C-H
Rev. 1.4, 2007-02
4
03062006-GD6J-14FP