HYS72T128001HR Datasheet, PDF (20/40 Pages) Qimonda AG – 240-Pin Registered DDR SDRAM Modules

Internet Data Sheet
'46
'46 
&.
&.
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 3
Differential input waveform timing - t_DS and t_DS
W'6 W'+
W'6  W'+
9_' _{'4 }
9_,_+DF _PLQ 
9_,_+GF _PLQ 
9₅ _()GF
9_,_/GF _PD[ 
9_,_/DF _PD[ 
9₆ _6
FIGURE 4
Differential input waveform timing - t_lS and t_lH
W,6  W,+ 
W,6 W,+ 
9_' _{'4 }
9_,_{+DF }PLQ
9_,_{+GF }PLQ
9₅ _()GF
9_,_{/GF }PD[ 
9_,_{/DF }PD[ 
9₆ _6
Rev. 1.4, 2007-02
20
03062006-GD6J-14FP