HYS72T128001HR Datasheet, PDF (32/40 Pages) Qimonda AG – 240-Pin Registered DDR SDRAM Modules

Product Type
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Organization
Label Code
JEDEC SPD Revision
Byte#
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Description
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W)
∆T_5B (DT5B)
∆T₇ (DT7)
Psi(ca) PLL
Psi(ca) REG
∆T_PLL (DTPLL)
∆T_REG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
2 GByte
2 GByte
1 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×8) 1 Rank (×4)
PC2–
PC2–
PC2–
PC2–
5300R–555 4200R–444 3200R–333 3200R–333
Rev. 1.2
Rev. 1.1
Rev. 1.2
Rev. 1.1
HEX
06
3C
7F
80
18
22
0F
50
58
37
21
21
24
23
17
4A
21
28
C4
8C
68
94
12
8F
7F
7F
HEX
06
3C
7F
80
1E
28
0F
51
60
37
1D
23
1E
1F
16
43
22
2A
C4
8C
61
78
11
A4
7F
7F
HEX
06
37
7F
80
23
2D
0F
51
60
33
1A
23
18
18
16
35
21
25
C4
8C
59
5C
12
D8
7F
7F
HEX
06
37
7F
80
23
2D
0F
51
60
33
1A
23
18
18
16
35
21
25
C4
8C
59
5C
11
D2
7F
7F
Rev. 1.4, 2007-02
32
03062006-GD6J-14FP