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HYS72T128001HR Datasheet, PDF (28/40 Pages) Qimonda AG – 240-Pin Registered DDR SDRAM Modules
Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol Note
1)2)3)4)5)6)
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3N
IDD3P(0)
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Distributed Refresh Current
IDD5D
tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 18
4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6) For details and notes see the relevant Qimonda component data sheet
Parameter
LOW
STABLE
FLOATING
SWITCHING
Description
TABLE 18
Definitions for IDD
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are VREF = VDDQ /2
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Rev. 1.4, 2007-02
28
03062006-GD6J-14FP