HYB18H256321BF Datasheet, PDF (34/41 Pages) Qimonda AG – 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM

Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
Parameter
CAS latency
Symbol Limit Values
Unit Note
–10
–11
–12
–14
Min. Max. Min. Max. Min. Max. Min. Max.
Data-in and Data Mask to WDQS Setup t_DS
Time
0.14 — 0.15 — 0.16 — 0.18 — ns
Data-in and Data Mask to WDQS Hold t_DH
Time
0.14 — 0.15 — 0.16 — 0.18 — ns
Data-in and DM input pulse width (each t_DIPW 0.40 — 0.40 — 0.40 — 0.40 — t_CK
input)
DQS input low pulse width
t_DQSL
0.40 —
0.40 —
0.40 —
0.40 —
t_CK
DQS input high pulse width
t_DQSH 0.40 —
0.40 —
0.40 —
0.40 —
t_CK
DQS Write Preamble Time
t_WPRE 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t_CK
DQS Write Postamble Time
t_WPST 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t_CK
Write Recovery Time
t_WR
13 —
13 —
12 —
10
—
t_CK ⁸⁾
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
t_AC
-0.21 0.21 -0.22 0.22 -0.22 0.22 –0.25 0.25 ns
Read Preamble
t_RPRE 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t_CK
Read Postamble
t_RPST 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t_CK
Data-out high impedance time from CLK t_HZ
t_ACmin t_ACmax t_ACmin t_ACmax t_ACmin t_ACmax t_ACmin t_ACmax ns
Data-out low impedance time from CLK t_LZ
t_ACmin t_ACmax t_ACmin t_ACmax t_ACmin t_ACmax t_ACmin t_ACmax ns
DQS edge to Clock edge skew
t_DQSCK -0.21 0.21 -0.22 0.22 -0.22 0.22 –0.25 0.25 ns
DQS edge to output data edge skew
t_DQSQ — 0.120 — 0.130 — 0.140 —
0.160 ns ¹¹⁾
Data hold skew factor
t_QHS
— 0.120 — 0.130 — 0.140 — 0.160 ns
Data output hold time from DQS
t_QH
t_HP–t_QHS
ns
Refresh/Power Down Timing
Refresh Period (8192 cycles)
t_REF
Average periodic Auto Refresh interval t_REFI
Delay from AREF to next ACT/ AREF t_RFC
Self Refresh Exit time
t_XSC
Power Down Exit time
t_XPN
Other Timing Parameters
— 32 — 32 — 32 — 32 ms
3.9
3.9
3.9
3.9
μs
52.0 — 52.0 — 52.0 — 52.0 — ns
1000 — 1000 — 1000 — 1000 — t_CK
7
—7
—7
—6
—
t_CK
RES to CKE setup timing
t_ATS
10 — 10 — 10 — 10 — ns
RES to CKE hold timing
t_ATH
10 — 10 — 10 — 10 — ns
Termination update Keep Out timing
t_KO
10 — 10 — 10 — 10 — ns
Rev. ID EMRS to DQ on timing
t_RIDon
—
20
—
20
—
20
—
20
ns
Rev. ID EMRS to DQ off timing
t_RIDoff
—
20
—
20
—
20
—
20
ns
1) DLL on mode ( -10/-11/-12/-14 f_CK(Min )= 400 MHz)
2) DLL on mode ( -10/-11/-12/-14 f_CK(Min )= 400 MHz)
3) t_HP is the lesser of t_CL minimum and t_CH minimum actually applied to the device CLK, CLK inputs
4) This value of tMRD applies only to the case where the “DLL reset” bit is not activated
5) t_MRD is defined from MRS to any other command then READ
6) t_RASmax is 8*t_REF
7) t_RCDWR(Min) may not drop below 2 × t_CK
Rev. 0.80, 2007-09
34
09132007-07EM-7OYI