HYB18H256321BF Datasheet, PDF (18/41 Pages) Qimonda AG – 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM

Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
FIGURE 8
Extended Mode Register Bitmap for High-Speed Application
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Notes
1. These settings are for debugging purposes only.
2. Default termination values at Power Up.
3. The ODT disable function disables all terminators on the
device.
4. If the user activates bits in the extended mode register in
an optional field, either the optional field is activated (if
option implemented in the device) or no action is taken by
the device (if option not implemented).
5. WR (write recovery time for auto precharge) in clock
cycles is calculated by dividing t_WR (in ns) and rounding up
to the next integer (WR[cycles] = t_WR[ns] / t_CK[ns]). The
mode register must be programmed to this value.
CLK#
CLK
Command
PA
NOP
t_RP
FIGURE 9
Extended Mode Register Set Timing
EMRS
NOP
t_MRD
NOP
A.C.
A.C.: Any command
Don't Care
EMRS: Extended MRS command
PA: PREALL command
Rev. 0.80, 2007-09
18
09132007-07EM-7OYI