HYB18H256321BF Datasheet, PDF (21/41 Pages) Qimonda AG – 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM

Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
3.3
Extended Mode Register 2 Set Command (EMRS2)
FIGURE 11
Extended Mode Register 2 Set Command
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The Extended Mode Register 2 is used to define the active
bitmap of the Mode Register and the Extended Mode
Register. The Extended Mode Register 2 must be written
after power up to operate the GDDR3 Graphics RAM. The
Extended Mode Register 2 can be programmed by
performing a normal Mode Register Set operation and setting
the BA1 bit to HIGH and BA0 bits to LOW. All bits defined as
RFU in the bitmap are reserved and must be set to LOW. The
Extended Mode Register 2 must be loaded when all banks
are idle and no burst are in progress. The controller must wait
the specified time t_MRD before initiating any subsequent
operation. The timing of the EMRS2 command operation is
equivalent to the timing of the MRS command operation.
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FIGURE 12
Extended Mode Register 2 Bitmap
 
 
 




















 



 
Rev. 0.80, 2007-09
21
09132007-07EM-7OYI