HYB25D512400C Datasheet, PDF (31/37 Pages) Qimonda AG – DDR SDRAM

Internet Data Sheet
HYB25D512[400/160/800]C[E/T/F/C](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 22
I_DD Specification for HYB25D512[400/160/800]C[EF](L)
–6
–5
Unit
Note¹⁾
DDR333
DDR400B
Symbol
Typ.
Max.
Typ.
Max.
I_DD0
60
70
60
75
mA
×4/×8 ²⁾³⁾
70
85
75
90
mA
×16 ³⁾
I_DD1
65
80
70
85
mA
×4/×8 ³⁾
80
95
90
110
mA
×16 ³⁾
I_DD2P
I_DD2F
I_DD2Q
I_DD3P
I_DD3N
1.1
4.6
21
25
15
22
11
15
32
37
33
40
1.1
4.6
25
30
17
23
12
16
35
42
38
45
mA
3)
mA
3)
mA
3)
mA
3)
mA
×4/×8³⁾
mA
×16 ³⁾
I_DD4R
70
85
95
115
80
90
110
135
mA
×4/×8 ³⁾
mA
×16 ³⁾
I_DD4W
75
90
100
120
85
95
115
135
mA
×4/×8 ³⁾
mA
×16 ³⁾
I_DD5
130
175
145
190
mA
3)
I_DD6
1.6
5
1.6
5
mA
4)
—
2.5
—
2.5
mA
low power part(L)
I_DD7
175
205
195
230
mA
×4/×8³⁾
190
230
210
250
mA
×16 ³⁾
1) Test conditions for typical values: V_DD = 2.5 V (DDR333), V_DD = 2.6 V (DDR400), T_A = 25 °C, test conditions for maximum values:
V_DD = 2.7 V, T_A = 10 °C
2) I_DD specifications are tested after the device is properly initialized and measured at 166 MHz for DDR333, and 200 MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
Rev. 1.31, 2006-09
31
03292006-3TFJ-HNV3