HYS72T512420EFA Datasheet, PDF (28/37 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products

Internet Data Sheet
HYS72T512420EFA–[25F/3S]–C
Fully-Buffered DDR2 SDRAM Modules
Product Type
HYS72T512420EFA–3S–C
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Description
HEX
SPD Size CRC / Total / Used
92
SPD Revision
11
Key Byte / DRAM Device Type
09
Voltage Level of this Assembly
12
SDRAM Addressing
49
Module Physical Attributes
23
Module Type
07
Module Organization
10
Fine Timebase (FTB) Dividend and Divisor
00
Medium Timebase (MTB) Dividend
01
Medium Timebase (MTB) Divisor
04
t_CK.MIN (min. SDRAM Cycle Time)
0C
t_CK.MAX (max. SDRAM Cycle Time)
20
CAS Latencies Supported
33
t_CAS.MIN (min. CAS Latency Time)
3C
Write Recovery Values Supported (WR)
42
t_WR.MIN (Write Recovery Time)
3C
Write Latency Times Supported
72
Additive Latency Times Supported
50
t_RCD.MIN (min. RAS# to CAS# Delay)
3C
t_RRD.MIN (min. Row Active to Row Active Delay)
1E
t_RP.MIN (min. Row Precharge Time)
3C
t_RAS and t_RC Extension
00
t_RAS.MIN (min. Active to Precharge Time)
B4
t_RC.MIN (min. Active to Active / Refresh Time)
F0
t_RFC.MIN LSB (min. Refresh Recovery Time Delay)
FE
t_RFC.MIN MSB (min. Refresh Recovery Time Delay)
01
t_WTR.MIN (min. Internal Write to Read Cmd Delay)
1E
t_RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
03
Rev.1.20, 2007-10-19
28
03202007-06NE-DYYI
TABLE 17
PC2–5300–555