HYS72T512420EFA Datasheet, PDF (19/37 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products

Internet Data Sheet
HYS72T512420EFA–[25F/3S]–C
Fully-Buffered DDR2 SDRAM Modules
5
Current Spec. and Conditions
The following table provides an overview of the measurement conditions.
Parameter
TABLE 13
I_DD Measurement Conditions
Symbol
Idle Current, single or last DIMM
L0 state, idle (0 BW)
Primary channel enabled, Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active
I_{CC_Idle_0}
I_{DD_Idle_0}
Idle Current, first DIMM
L0 state, idle (0 BW)
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active
I_{CC_Idle_1}
I_{DD_Idle_1}
Active Power
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
I_{CC_Active_1}
I_{DD_Active_1}
Training
Primary and Secondary channels enabled.
100% toggle on all channels lanes.
DRAMs idle (0 BW).
CKE high. Command and address lines stable.
DRAM clock active.
I_{CC_Training}
I_{DD_Training}
IBIST
Over all IBIST modesDRAM Idle (0 BW)Primary channel EnabledSecondary channel EnabledCKE high.
Command and Address lines stableDRAM clock active
I_{CC_IBIST}
I_{DD_IBIST}
MemBIST
Over all MemBIST modes >50% DRAM BW (as dictated by the AMB)Primary channel EnabledSecondary
channel EnabledCKE high. Command and Address lines stableDRAM clock active
I_{CC_MEMBIST}
I_{DD_MEMBIST}
Electrical Idle
I_{CC_EI}
DRAM Idle (0 BW)Primary channel DisabledSecondary channel DisabledCKE low. Command and Address I_{DD_EI}
lines FloatedDRAM clock active, ODT and CKE driven low
Notes
1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB
2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.
3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.
4. Burst Length = 4.
5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).
6. Modeled with 27 Ω termination for command, address, and clocks, and 47 Ω termination for control.
7. Termination is referenced to V_TT = V_DD / 2.
Rev.1.20, 2007-10-19
19
03202007-06NE-DYYI