HYS72T512420EFA Datasheet, PDF (25/37 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products

Internet Data Sheet
HYS72T512420EFA–[25F/3S]–C
Fully-Buffered DDR2 SDRAM Modules
Product Type
HYS72T512420EFA–25F–C
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–6400F–555
JEDEC SPD Revision
Rev. 1.1
Byte# Description
HEX
21
t_RP.MIN (min. Row Precharge Time)
32
22
t_RAS and t_RC Extension
00
23
t_RAS.MIN (min. Active to Precharge Time)
B4
24
t_RC.MIN (min. Active to Active / Refresh Time)
D2
25
t_RFC.MIN LSB (min. Refresh Recovery Time Delay)
FE
26
t_RFC.MIN MSB (min. Refresh Recovery Time Delay)
01
27
t_WTR.MIN (min. Internal Write to Read Cmd Delay)
1E
28
t_RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
29
Burst Lengths Supported
03
30
Terminations Supported
07
31
Drive Strength Supported
01
32
t_REFI (avg. SDRAM Refresh Period)
C2
33
T_CASE.MAX Delta / ΔT_4R4W Delta
57
34
Psi(T-A) DRAM
60
35
ΔT₀ (DT0) DRAM
5C
36
ΔT_2Q (DT2Q) DRAM
29
37
ΔT_2P (DT2P) DRAM
2B
38
ΔT_3N (DT3N) DRAM
2E
39
ΔT_4R (DT4R) / ΔT_4R4W Sign (DT4R4W) DRAM
4E
40
ΔT_5B (DT5B) DRAM
25
41
ΔT₇ (DT7) DRAM
39
42 - 78 Not used
00
79
FBDIMM ODT Values
21
80
Not used
00
81
Channel Protocols Supported LSB
02
82
Channel Protocols Supported MSB
00
83
Back-to-Back Access Turnaround Time
20
84
AMB Read Access Delay for DDR2-800
54
85
AMB Read Access Delay for DDR2-667
50
86
AMB Read Access Delay for DDR2-533
44
87
Psi(T-A) AMB
26
88
ΔT_{Idle_0} (DT Idle_0) AMB
3F
89
ΔT_{Idle_1} (DT Idle_1) AMB
50
Rev.1.20, 2007-10-19
25
03202007-06NE-DYYI