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HYS72T512422HFN Datasheet, PDF (27/41 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules | |||
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Product Type
Internet Data Sheet
HYS72T512[4/5]22HFNâ[3S/3.7]âA
240-Pin Fully-Buffered DDR2 SDRAM Modules
Organization
4 GByte
Ã72
2 Ranks (Ã4)
Label Code
PC2â5300Fâ555
JEDEC SPD Revision
Rev. 1.1
Byte#
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Description
HEX
tCAS.MIN (min. CAS Latency Time)
3C
Write Recovery Values Supported (WR)
42
tWR.MIN (Write Recovery Time)
3C
Write Latency Times Supported
72
Additive Latency Times Supported
50
tRCD.MIN (min. RAS# to CAS# Delay)
3C
tRRD.MIN (min. Row Active to Row Active Delay)
1E
tRP.MIN (min. Row Precharge Time)
3C
tRAS and tRC Extension
00
tRAS.MIN (min. Active to Precharge Time)
B4
tRC.MIN (min. Active to Active / Refresh Time)
F0
tRFC.MIN LSB (min. Refresh Recovery Time Delay)
FE
tRFC.MIN MSB (min. Refresh Recovery Time Delay)
01
tWTR.MIN (min. Internal Write to Read Cmd Delay)
1E
tRTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
03
Terminations Supported
07
Drive Strength Supported
01
tREFI (avg. SDRAM Refresh Period)
C2
TCASE.MAX Delta / âT4R4W Delta
50
Psi(T-A) DRAM
58
âT0 (DT0) DRAM
34
âT2Q (DT2Q) DRAM
21
âT2P (DT2P) DRAM
21
âT3N (DT3N) DRAM
24
âT4R (DT4R) / âT4R4W Sign (DT4R4W) DRAM
4A
Rev. 1.3, 2006-12
27
03292006-QQ89-IKE4
4 GByte
Ã72
2 Ranks (Ã4)
PC2â5300Fâ555
Rev. 1.1
HEX
3C
42
3C
72
50
3C
1E
3C
00
B4
F0
FE
01
1E
1E
03
07
01
C2
50
58
34
21
21
24
4A
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