HYS72T512422HFN Datasheet, PDF (14/41 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T512[4/5]22HFN–[3S/3.7]–A
240-Pin Fully-Buffered DDR2 SDRAM Modules
FIGURE 3
Block Diagram of Channel Southbound and Northbound Paths
6RX WKE RXQG 
+R VW
$0%
1R XUWKER XQG
$0%
$0%
$0%
QF
03 %7 
QF
3.3
High-Speed Differential Point-to-Point Link (at 1.5 V)
Interfaces
The Advanced Memory Buffer supports one FB-DIMM
Channel consisting of two bidirectional link interfaces using
highspeed differential point-to-point electrical signaling. The
southbound input link is 10 lanes wide and carries commands
and write data from the host memory controller or the
adjacent DIMM in the host direction. The southbound output
link forwards this same data to the next FB-DIMM. The
northbound input link is 14 lanes wide and carries read return
data or status information from the next FB-DIMM in the chain
back towards the host. The northbound output link forwards
this information back towards the host and multiplexes in any
read return data or status information that is generated
internally. Data and commands sent to the DRAMs travel
southbound on 10 primary differential signal line pairs. Data
received from the DRAMs and status information travel
northbound on 14 primary differential pairs. Data and
commands sent to the adjacent DIMM upstream are repeated
and travel further southbound on 10 secondary differential
pairs. Data and status information received from the adjacent
DIMM upstream travel further northbound on 14 secondary
differential pairs.
3.3.1
DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports
direct connection to DDR2 SDRAMs. The DDR2 channel
supports two ranks of eight banks with 16 row/column
request, 64 data, and eight check-bit signals. There are two
copies of address and command signals to support DIMM
routing and electrical requirements. Four transfer bursts are
driven on the data and check-bit lines at 800 MHz.
Propagation delays between read data/check-bit strobe lanes
on a given channel can differ. Each strobe can be calibrated
by hardware state machines using write/read trial and error.
Rev. 1.3, 2006-12
14
03292006-QQ89-IKE4