HYS72T512422HFN Datasheet, PDF (26/41 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T512[4/5]22HFN–[3S/3.7]–A
240-Pin Fully-Buffered DDR2 SDRAM Modules
6
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
• Table 16 “PC2–5300F–555” on Page 26
• Table 17 “PC2–4200F–444” on Page 31
Product Type
TABLE 16
PC2–5300F–555
Organization
Label Code
JEDEC SPD Revision
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Description
SPD Size CRC / Total / Used
SPD Revision
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
Module Physical Attributes
Module Type
Module Organization
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
t_CK.MIN (min. SDRAM Cycle Time)
t_CK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
Rev. 1.3, 2006-12
03292006-QQ89-IKE4
4 GByte
×72
2 Ranks (×4)
PC2–5300F–555
Rev. 1.1
HEX
92
11
09
12
49
23
07
10
00
01
04
0C
20
33
26
4 GByte
×72
2 Ranks (×4)
PC2–5300F–555
Rev. 1.1
HEX
92
11
09
12
49
23
07
10
00
01
04
0C
20
33