HYS72T512422HFN Datasheet, PDF (21/41 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T512[4/5]22HFN–[3S/3.7]–A
240-Pin Fully-Buffered DDR2 SDRAM Modules
Parameter
MemBIST
Over all MemBIST modes >50% DRAM BW (as dictated by the AMB)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Address lines stable
DRAM clock active
Electrical Idle
DRAM Idle (0 BW)
Primary channel Disabled
Secondary channel Disabled
CKE low. Command and Address lines Floated
DRAM clock active, ODT and CKE driven low
Symbol
I_{CC_MEMBIST}
I_{DD_MEMBIST}
I_{CC_EI}
I_{DD_EI}
Notes
1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB
2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.
3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.
4. Burst Length = 4.
5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).
6. Modeled with 27 Ω termination for command, address, and clocks, and 47 Ω termination for control.
7. Termination is referenced to V_TT = V_DD / 2.
In the following table you can find the Measurement Conditions and Power Supply Currents¹⁾²⁾
Product Type
TABLE 14
I_CC/I_DD Specification for PC2-5300F
Unit
Note
Speed Grade
Symbol
ICC_Idle_0
PCC_Idle_0
IDD_Idle_0
PDD_Idle_0
ITOT_Idle_0
PTOT_Idle_0
PC2-5300F
PC2-5300F
Typ.
Typ.
2.16
2.06
A
3.27
3.12
W
2.33
2.15
A
4.1
3.79
W
4.52
4.25
A
7.4
6.95
W
1) Measured currents on raw card A/B/H/D according to the INTEL/ JEDEC specifcation.The measurements are done in a INTEL Blackford
system.
2) The Power is calculated as follows: P_cc = V_cc x I_cc where V_cc = 1.5 V
Rev. 1.3, 2006-12
21
03292006-QQ89-IKE4