HYS72T256322HP Datasheet, PDF (25/36 Pages) Qimonda AG – 240-Pin Dual-Die Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.4
Currents Specifications and Conditions
This chapter contains the Specifications and Conditions.
Parameter
TABLE 18
I_DD Measurement Conditions
Symbol Note^{1)2)3)4)5)6)7)8)}
Operating Current 0
I_DD0
One bank Active - Precharge; t_CK = t_CK.MIN, t_RC = t_RC.MIN, t_RAS = t_RAS.MIN, CKE is HIGH, CS is
HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs
are SWITCHING.
Operating Current 1
I_DD1
One bank Active - Read - Precharge; I_OUT = 0 mA, BL = 4, t_CK = t_CK.MIN, t_RC = t_RC.MIN, t_RAS =
t_RAS.MIN, t_RCD = t_RCD.MIN, AL = 0, CL = CL_.MIN; CKE is HIGH, CS is HIGH between valid
commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK.MIN; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING
I_DD2N
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING_.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK.MIN; Other control and address inputs are
STABLE, Data bus inputs are FLOATING.
I_DD2P
I_DD2Q
Active Power-Down Current
I_DD3P(0)
All banks open; t_CK = t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
I_DD3P(1)
All banks open; t_CK = t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Active Standby Current
I_DD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CK.MIN;
t_RAS = t_RAS.MAX, t_RP = t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING; I_OUT = 0 mA.
Operating Current
I_DD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CK.MIN;
t_RAS = t_RAS.MAX., t_RP = t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING; I_OUT = 0 mA.
Operating Current
I_DD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CK.MIN;
t_RAS = t_RAS.MAX., t_RP = t_RP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t_CK = t_CK.MIN., Refresh command every t_RFC = t_RFC.MIN interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
I_DD5B
Distributed Refresh Current
t_CK = t_CK.MIN, Refresh command every t_RFC = t_REFI interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
I_DD5D
Rev. 1.01, 2006-09
26
03062006-PK3L-ZYSE