HYS72T256322HP Datasheet, PDF (17/36 Pages) Qimonda AG – 240-Pin Dual-Die Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.3.2
AC Timing Parameters
This chapter contains the AC Timing Parameters.
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Min.
Max.
Unit
Note^{1)2)3)4)5)6)7)}
8)
DQ output access time from CK / CK
t_AC
DQS output access time from CK / CK
t_DQSCK
Average clock high pulse width
t_CH.AVG
Average clock low pulse width
t_CL.AVG
Average clock period
t_CK.AVG
DQ and DM input setup time
t_DS.BASE
DQ and DM input hold time
t_DH.BASE
Control & address input pulse width for each input t_IPW
DQ and DM input pulse width for each input
t_DIPW
Data-out high-impedance time from CK / CK
t_HZ
DQS/DQS low-impedance time from CK / CK
t_LZ.DQS
DQ low impedance time from CK/CK
t_LZ.DQ
DQS-DQ skew for DQS & associated DQ signals t_DQSQ
CK half pulse width
t_HP
DQ hold skew factor
t_QHS
DQ/DQS output hold time from DQS
t_QH
Write command to DQS associated clock edges WL
DQS latching rising transition to associated clock t_DQSS
edges
–450
–400
0.48
0.48
3000
100
175
0.6
0.35
—
t_AC.MIN
2 x t_AC.MIN
—
Min(t_CH.ABS,
t_CL.ABS)
—
t_HP – t_QHS
RL–1
– 0.25
+450
+400
0.52
0.52
8000
––
––
—
—
t_AC.MAX
t_AC.MAX
t_AC.MAX
240
__
340
—
+ 0.25
ps
ps
t_CK.AVG
t_CK.AVG
ps
ps
ps
t_CK.AVG
t_CK.AVG
ps
ps
ps
ps
ps
9)
9)
10)11)
10)11)
12)13)14)
13)14)15)
9)16)
9)16)
9)16)
17)
18)
ps
19)
ps
20)
nCK
t ²¹⁾
CK.AVG
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
CAS to CAS command delay
Write recovery time
Auto-Precharge write recovery + precharge time
Internal write to read command delay
t_DQSH
t_DQSL
t_DSS
t_DSH
t_WPST
t_WPRE
t_IS.BASE
t_IH.BASE
t_RPRE
t_RPST
t_CCD
t_WR
t_DAL
t_WTR
0.35
—
0.35
—
0.2
—
0.2
—
0.4
0.6
0.35
—
200
—
275
—
0.9
1.1
0.4
0.6
2
—
15
—
WR + t_nRP
—
7.5
—
t_CK.AVG
t_CK.AVG
t_CK.AVG
t_CK.AVG
t_CK.AVG
t_CK.AVG
ps
ps
t_CK.AVG
t_CK.AVG
nCK
ns
nCK
ns
21)
21)
22)23)
23)24)
25)26)
25)27)
1)
28)29)
1)30)
Rev. 1.01, 2006-09
18
03062006-PK3L-ZYSE