PE9763 Datasheet, PDF (7/15 Pages) Peregrine Semiconductor Corp. – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE9763
Product Specification
Table 6. AC Characteristics
V_DD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
fClk
tClkH
tClkL
tDSU
tDHLD
tPW
tCWR
tCE
tWRC
tEC
Fin
PFin
Fin
PFin
fr
Pfr
fc
Φ_N
Φ_N
Parameter
Conditions
Min
Typ
Max
Control Interface and Latches (see Figures 3, 4)
Serial data clock frequency
(Note 1)
10
Serial clock HIGH time
30
Serial clock LOW time
30
Sdata set-up time to Sclk rising edge
10
Sdata hold time after Sclk rising edge
10
S_WR pulse width
30
Sclk rising edge to S_WR rising edge
30
Sclk falling edge to E_WR transition
30
S_WR falling edge to Sclk rising edge
30
E_WR transition to Sclk rising edge
30
Main Divider (Including Prescaler) (Note 4)
Operating frequency
275
3200
Input level range
External AC coupling
-5
5
Main Divider (Prescaler Bypassed) (Note 4)
Operating frequency
50
300
Input level range
External AC coupling
-5
5
Reference Divider
Operating frequency
(Note 3)
100
Reference input power (Note 2)
Single ended input
-2
Phase Detector
Comparison frequency
(Note 3)
50
SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 10 MHz, LBW = 50 kHz, VDD = 3.0 V, Temp = 25° C) (Note 4)
Phase Noise
1 kHz Offset
-88
Phase Noise
10 kHz Offset
-92
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
dBm
MHz
dBm
MHz
dBm
MHz
dBc/Hz
dBc/Hz
Note 1:
Note 2:
Note 3:
Note 4:
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Parameter below are not tested for die sales. These parameters are verified during the element evaluation per the die flow.
Document No. 70-0140-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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