PE9763 Datasheet, PDF (4/15 Pages) Peregrine Semiconductor Corp. – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE9763
Product Specification
Pin No.
46
47
Pin
Name
VDD
VDD
Fin
Valid
Mode
Both
Type
(Note 1)
(Note 1)
Input
Description
ESD VDD.
Prescaler VDD.
Prescaler input from the VCO. 3.2 GHz max frequency.
48
F_in
GND
Both
Input
Downbond
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 Ω resistor directly to the ground plane.
Prescaler ground.
49
GND
Downbond Prescaler ground.
GND
50
CEXT
51
LD
52
DOUT
Both
Both
Both
Downbond
Output
Output
Output
Output driver/charge pump ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Data out function, enabled in enhancement mode.
53
VDD
(Note 1)
Output driver/charge pump VDD.
54
GND
55
PD_D
56
CP
57
PD_U
Both
Both
Both
Downbond
Output
Output
Output
Output driver/charge pump ground.
PD_D pulses down when fp leads fc. PD_U is driven to GND when CPSEL = “High”.
Charge pump output. Selected when CPSEL = “1”. Tristate when CPSEL = “Low”.
PD_U pulses down when fc leads fp. PD_D is driven to GND when CPSEL = “High”.
58
GND
Downbond Output driver/charge pump ground.
59
VDD
(Note 1)
Output driver/charge pump VDD.
GND
Downbond Phase detector GND.
VDD
60
VDD
(Note 1)
(Note 1)
Phase detector VDD.
ESD VDD.
GND
61
GND
62
fr
Both
Downbond
Downbond
Input
ESD ground.
Reference ground.
Reference frequency input.
63
VDD
(Note 1)
Reference VDD.
64
VDD
(Note 1)
Digital core VDD.
GND
Downbond Digital core ground.
65
ENH
Both
66
CPSEL
Both
67
MS2_SEL ^Both
Input
Input
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
Charge pump select. “High” enables the charge pump and disables pins PD_U and PD_D by
forcing them “low”. A “low” Tri-states the CP and enables PD_U and PD_D.
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
68
Note 1:
Note 2:
RND_SEL Both
Input
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 2¹⁹.
All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
All digital input pins have 70 kΩ pull-down resistors to ground.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0140-02 │ UltraCMOS™ RFIC Solutions