PE9763 Datasheet, PDF (12/15 Pages) Peregrine Semiconductor Corp. – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE9763
Product Specification
Phase Detector and Charge Pump
The phase detector is triggered by rising edges
from the main Counter (f_p) and the reference
counter (f_c). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (f_p leads f_c),
PD_D pulses “low”. If the divided reference leads
the divided VCO in phase or frequency (f_c leads
f_p), PD_U pulses “low”. The width of either pulse
is directly proportional to phase offset between the
two input signals, f_p and f_c.
For the UP and DOWN mode, PD_U and PD_D
drive an active loop filter which controls the VCO
tune voltage. The phase detector gain is equal to
VDD / 2 п.
PD_U pulses cause an increase in VCO fre-
quency and PD_D pulses cause a decrease in
VCO frequency, for a positive Kv VCO.
For the charge pump mode, the phase detector
outputs are used internally to drive a tri-state
charge pump. However, the PD_U, and PD_D out-
put pins will be drive statically to GND. The
charge pump will drive a fixed 2 mA of current.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kΩ resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal in-
verting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
Figure 5. Typical Phase Noise
A typical phase noise plot is shown below. Phase noise results for “Trace 2” is the average values.
Test Conditions: Fout = 1.9202 GHz, Fcomparison = 20 MHz, MASH 1-1, V_DD = 3 V, Temp = 25 C,
Loop bandwidth = 80 KHz.
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Document No. 70-0140-02 │ UltraCMOS™ RFIC Solutions