PE9763 Datasheet, PDF (3/15 Pages) Peregrine Semiconductor Corp. – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE9763
Product Specification
Pin No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Pin
Name
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
VDD
VDD
GND
GND
M0
M1
M2
M3
M4
S_WR
M5
34
SDATA
M6
35
SCLK
36
M7
37
M8
38
A0
A1
39
E_WR
40
A2
41
A3
42
DIRECT
43
Pre_en
44
VDD
GND
45
GND
Valid
Mode
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Serial
Direct
Serial
Direct
Serial
Direct
Direct
Direct
Direct
Serial
Direct
Direct
Both
Direct
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Downbond
Downbond
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Downbond
Downbond
Description
K Counter bit7.
K Counter bit8.
K Counter bit9.
K Counter bit10.
K Counter bit11.
K Counter bit12.
K Counter bit13.
K Counter bit14.
K Counter bit15.
K Counter bit16.
K Counter bit17 (MSB).
Digital core VDD.
ESD VDD.
Digital core ground.
ESD ground.
M Counter bit0 (LSB).
M Counter bit1.
M Counter bit2
M Counter bit3.
M Counter bit4.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
M Counter bit5.
Binary serial data input. Input data entered MSB first.
M Counter bit6.
Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR “low”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
M Counter bit7.
M Counter bit8 (MSB).
A Counter bit0 (LSB).
A Counter bit1.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
A Counter bit2.
A Counter bit3 (MSB).
Direct mode select. “High” enables direct mode. “Low” enables serial mode.
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Digital core VDD.
Digital core ground.
ESD ground.
Document No. 70-0140-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 15