PE9763 Datasheet, PDF (11/15 Pages) Peregrine Semiconductor Corp. – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE9763
Product Specification
Figure 4. Serial Interface Mode Timing Diagram
Sdata
E_WR
t_EC
Sclk
S_WR
t_DSU
t_DHLD
t_ClkH
t_ClkL
t_CE
t_CWR
t_PW
t_WRC
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 10. Enhancement Register Bit Functionality
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit Function
Reserve **
Reserve **
fp output
Power down
Counter load
MSEL output
fc output
LD Disable
Description
Reserved.
Reserved.
Drives the M counter output onto the Dout output.
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the reference counter output onto the Dout output.
Disables the LD pin for quieter operation.
** Program to 0
Document No. 70-0140-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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